With the emergence of the laptop computer market, there has been a desire for a new Personal Computer (PC) that operates at a very low power. Although recently the PC market has been attempting to move to power supply voltages of 3 volts, instead of the 5 volts, the focus of reducing power consumption has been in the area of when the chip is in a state of little or no activity. Ideally, when a chip is not active currently, it would be beneficial to reduce the power consumption, thereby operating at a lower power than if the chip was constantly drawing power. One method of achieving low power consumption in chips is to employ power management circuits. Power management circuits put the chip into a state that draws little or no current, even though the supply voltage remains coupled to the chip. This state is known as power down. Power management circuits are particularly advantageous to utilize when a chip is not currently active.
One type of prior art power management circuit utilizes external counters to detect activity in the chip. These counters are usually timers keyed to the last access of the chip. These timers act as retriggerable one-shots, such that when no activity occurs for a predetermined period of time, the chip is allowed to power down. One problem with such a power management scheme is that external control (i.e., via the counter) of the power management circuit is required. When the external counters signal that the chip may be put into power down mode, an external switch switches off the power. Hence, actually entering the power down mode is externally controlled. Furthermore, these power management circuits are not transparent to software controlling the chip. Once the power is turned off and the power down state has been entered, all internal status is lost. Upon powering up the chip, all lost status must be restored.
Another problem with prior art power management circuits is that any form of reset, software or hardware (e.g., a pin), usually resets the power down mode. Since the software resets occur in most application software and in the disk operating system (DOS), the power down mode is soon lost and is again dependent on the intervention of basic input/output system (BIOS), DOS or the application software to maintain the mode. Furthermore, resetting a chip results in losing the status. Therefore, resetting initializes the chip to a default state, different from the internal state (i.e., status) of the chip before the reset. Those different status bits must be restored after the reset.
Other prior art power management circuits, such as National Semiconductors PC8477, have a power down mode which requires that the mode be restored when waking the chip back up again. Moreover, prior art power management circuits do not allow the user to program whether on-chip crystal oscillators are on or off when the rest of the chip is powered down. Typically, all prior art power management circuits turn the oscillator off and, thus, have problems with recovery time and start-up when powering up.
Another type of prior art power management circuit, such as those employed by Intel's 82077AA reduces the power to very low levels, but requires the BIOS, DOS or application software to control when the chip is placed in the power down. Further, these power management circuits require considerable software and time to restore the state of the internal machine to its pre-power down condition. Lastly, the crystal oscillator is powered down with the rest of the chip. When the crystal oscillator is powered down, the recovery is not well controlled and the time to recover could be very long.
As will be seen, the present invention provides an apparatus and method for a chip to monitor its own activity and enter and exit the power down state in a manner that is transparent to the software running the chip. Moreover, the present invention allows the oscillator to run making recovery time effectively instantaneous.